Transistors are formed in both digital and analog areas of an integrated circuit (IC). Transistors are typically formed by providing an active area with doped source/drain regions in the substrate, a gate insulating layer over the substrate, and a gate electrode over the gate insulating layer. Contacts connect the source/drain regions and gate electrodes with a conductive interconnect structure having several horizontal conductive pattern layers and vertical via layers formed within a plurality of inter-metal dielectric (IMD) layers.
As IC dimensions shrink, transistor design shift to a three-dimensional design with multiple gates, specifically fin field-effect transistors (FinFETs). FinFET devices typically include a number of semiconductor fins having high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of a portion of the semiconductor fins.
Because FinFETs are three-dimensional, the effective widths are larger than a corresponding planar transistor. In addition to the width of the active area, the effective FinFET width also includes two times the protruded portion of the fins, namely the height of the fins. In other words, the protruded portion of the fins adds to the effective width of the FinFET. The use of fins increases surface areas of the channel and source/drain regions for the same surface area. The increased surface area of the in a FinFET results in faster, more reliable and better-controlled semiconductor transistor devices that consume less power.
While FinFET devices provide improved characteristics, design improvements that reduce effect of mass-production processes continue to be sought.